OpenSource GPS Open Source Software for Learning about GPS

Teaching the next generation of engineers about the inner workings of GPS receivers is difficult due to the expense of acquiring appropriate hardware and software. In the past few years a number of excellent books have been written about GPS (references 1 through 5). But, in the end students learn best by doing. Even with hardware available, trying to squeeze the development of software into a quarter or a semester is asking a lot. A low cost set of hardware, along with free open source software, allows students access to the inner workings of the receiver without 'breaking the bank' in terms of time or money. This article will present open source GPS receiver software and laboratory hardware that is a straightforward modification of a COTS receiver to interface it to a PC bus. The hardware and software are based on the GEC Plessey, then Mitel, now Zarlink, chipset. In the 1990’s GEC introduced a board and software called the GPS Builder TM which placed the down converter and correlator chips on an ISA card installed on a PC. Since the software ran on the PC it gave the user complete control and visibility into the operation of the receiver. Unfortunately GEC and Mitel found that they had to charge in excess of $1000 dollars for the board and software licenses. This served to limit its popularity among cash strapped universities and individuals. Given the success of Linux, it was apparent that complex software development could be done on free open source software. This paper describes the hardware and software architecture, the features added to allow debugging of the code and carrier tracking loops, and plans for improving the software, install it on other receiver hardware, use embedded ‘x86 hardware, and to run under Open Source real time operating systems. A comparison will also be made of the software using two receivers, and will show the results of its performance. This is similar to experiments that students could perform using the open source software and hardware discussed herein. An Internet website has been set up at http://www.home.earthlink.net/~cwkelley to describe the project, and to provide source code and sample input and output data. HARDWARE GPS receiver hardware is complicated by the fact that there is RF signal processing in close vicinity to digital signals, which can interfere with the RF signal chain. In 1995 a 2-sided board was designed and built based on the GP 2020 chipset, which had 6 channels per chip. While it was possible to get it to work it was obvious that it had problems resetting and limited functionality. Building high quality 4 layer surface mount component boards is expensive and requires specialized test equipment. Another alternative was needed. While working with the Canadian Marconi AllStar and SuperStar it was noticed that it used the same chipset. Since the SuperStar OEM board is relatively inexpensive and well built it suggested the idea of “hacking” into the hardware to bypass the digital processing on the board, and connect directly into a PC. A description of how to do this is provided on the website. Since the SuperStar GP2021 interface is set up as a ‘186, the hardware was easy to setup. Although it destroys a perfectly good receiver, it seems to work well. Versions of the “hacked” receiver are working at both UCR and UNSW. Now, with hardware available for less than $200, adapting the software to the GP2021 was the only missing part. Figure 1 is a photograph of the hardware with the “hacked” receiver mounted to an ISA bus experimental card. Figure 1 Photograph of “hacked” GPS receiver As shown in Figure 2, the receiver consists of an RF "front end" chip and a digital processing chip connected to a PC I/O interface. The front end connects directly to the 10MHz clock and sends a 40MHz signal to the correlator chip. The correlator chip appears to the PC as a set of about 100 read and/or write registers. The RF signal is first down converted to about 175MHz, is sent to a simple band pass filter, and sent back to the front end. The second down converter stage is at about 35MHz. A SAW filter is used to filter and return the signal to the front end. In the final stage the signal is down converted to 4.3MHz and a 2-bit A/D converter (sign and magnitude) is used to transmit the signal information to the GP2021 correlator chip. The correlator chip provides the sample timing, which is simply the 40MHz clock divided by 7. The PC interface consists of an ISA I/O board from JDR Electronics set up to address two 16-bit ports. One port (0x304) uses the lower 8 bits to send the register address. The other port (0x308) is used to read and write 16 bits of data. The correlator chip interface can be set up in a number of ways. As it is set up as an Intel 186 interface an indeterminate amount of time is available between latching the address and transferring the data. 7404 RF cable MCX to SMA SMA bulkhead adapter Figure 2 Receiver Hardware Interface SOFTWARE OpenSource GPS is a C program written in Borland C (version 4.5 and later) without any embedded assembly language. As shown in Figure 3 the software uses a single interrupt routine to handle the tracking loops and find the navigation message. All other functions are handled using a polling method triggered by flags from the interrupt routine. Figure 4 shows the main software block diagram while Figure 5 illustrates in more detail the interrupt processing. In order to reduce connections to the correlator chip, the PC clock timing (interrupt 0) is taken over and is modified to provide an interrupt every 500 to 900μs. Figure 3 Software Block Diagram Figure 4 Main Program Figure 5 Interrupt Routine Figure 6 is a file structure diagram of the software. The program is written in three parts. GP2021 contains functions that deal with communication with the correlator chipset. The main routine is in gpsrcvr while gpsfuncs contains the library of GPS functions such as satellite location by using the almanac, ephemeris, computing the navigation solution and decoding the navigation message. The input file used only for input is the rcvr_par.dat file which contains constants used by the receiver, such as tracking loop constants for code and carrier for pull-in and tracking along with flags for various outputs. The input/output files are read at the start of the program and updated when the program exits. The output files record data for later analysis. Main Program Interrupt Service Routine Enable PC Clock Interrupt Generator Common Variables/ Flags Input Files Output Files I/O Files 512 μs delay Disable PC Clock Interrupt Generator Initialize